The primary difference between a DDR RAM and a DDR2 RAM is its preferch length. In the former, prefetch length was 2bits per bit in a single word while in DDR2 RAM, it’s 4 bits. During access, 4-bit deep prefetch queue was either written or read with 4 bits.
The queue then transmits or receives the data via data bus on two data bus clock cycles. With the increase prefetch length, it allows the DDR2 RAM to increase its rate to which data transfer in data bus without having to increase the rate of data transfer. DDR2 RAM design avoids excessive power consumption.
The improvements in electrical interfaces, prefetch buffers, off-chip drivers and on-chip termination have all helped in increasing the bus frequency of the new DDR2 RAM. Nevertheless, DDR2’s RAM significantly increases as part of its trade-off factor.
The depth of DDR2 prefetch buffer is 4 bits and 2 bits for DDR. Despite the fact that common 2 to 3 bus cycles is the common DDR SDRAM latency, the read latency for DDR2 might run from 3 to 9 cycles. On the other hand, common range is around 4 to 6. Having said that, DDR2 RAM should run twice the data rate in order to attain the same latency.